In the production of large scale integrated semiconductor chips, the ever increasing miniaturization of the structures on the semiconductor chip means that ever more exacting requirements are made of the fabrication installations and production processes used for the production of the semiconductor chips. The stability and reproducibility both of the fabrication installations and of the production processes influence the yield and productivity in the context of semiconductor chip fabrication. Even small deviations from a desired behavior of a chip fabrication installation in the context of production may lead to a considerable impairment of the yield, that is to say to a considerable increase in the defect rate for the semiconductor chips produced.
In order to ensure the quality of the semiconductor chips and to establish possible defects in a semiconductor chip, all the processed semiconductor chips have to be subjected to tests. Use has hitherto been made of functional tests, inter alia, which operate the semiconductor chip in a manner similar to the application and thus test it for fabrication defects. Since semiconductor chips comprise many individual electronic components, the individual electronic components are difficult to test by driving each individual electronic component separately with a test signal externally, since this would require far too many terminals on the chip.
In order to solve this problem, a scan test was introduced. During the scan test, all the components, that is to say digital gates, of all the chips produced are tested. To test the gates, a set of the storing components of a chip (flip-flops) are coupled to form a scan chain. In a scan chain, the individual flip-flops of the scan chain are connected in series with one another, one input terminal and one output terminal being available for the entire scan chain, by means of which the scan chain can be driven and read externally. During a first phase of the scan test, a shift phase, a test signal sequence is applied to the input terminal of the scan chain by means of a test system, a test signal sequence being shifted through the scan chain in clocked fashion. Overall, the number of clock cycles of the shift phase is equal in magnitude to the number of storing components (flip-flops) in the scan chain. After the end of the shift phase, a test signal is thus available at each storing component of the scan chain.
In a second phase of the scan test, the chip to be tested is operated in a normal mode for at least one clock cycle. In the normal mode, the chip is operated in accordance with its function. In this case, by means of the test signal provided at the respective storing components of the scan chain, a respective partial actual value signal is generated at a respective functional input of a storing component of the scan chain, the partial actual value signals of all the storing components of the scan chain forming an actual value signal.
During a third phase of the scan test, the output signals of the elements (the storing components of the scan chain) are shifted through the scan chain in clocked fashion and read out at the output terminal of the scan chain. The third phase of the scan test again has exactly the same number of clock cycles as the number of storing components in the scan chain.
After the end of such a cycle comprising the three phases described above, the actual value signal read out at the output terminal of the scan chain can be fed back to the test system. The test system had previously stored the signals of the test signal sequence, that is to say the input data (stimuli) which were applied to the storing components of the scan chain, and the associated desired value signal determined, that is to say the output data (expected responses) representing the reaction of the electronic components (digital gates) to be tested to the signals of the test signal sequence. Furthermore, the test system compares the actual value signal with a desired value signal to establish possibly defective electronic components of the semiconductor chip.
Consequently, by means of the standard scan test described above a large number of electronic components (digital gates) of a semiconductor chip can be tested with just one input terminal and one output terminal per scan chain. Known methods in the functional or scan based test proceed from generation, redistribution and decompression of input data situated on the electrical circuit.
DE 195 36 226 discloses a circuit arrangement with identical circuit blocks connected to one another in an arbitrary manner. In addition, the circuit arrangement has at least one input and one output terminal, in which, by means of a controlled switching device, the individual circuit blocks can be released from the connection to one another, can be coupled on the input side to a common input terminal for feeding in an input test pattern, and can be connected on the output side to an evaluation device for comparing the output test patterns of the individual circuit blocks.
It is known from “Halbleiter-Schaltungstechnik” [“Semiconductor circuitry”]; U. Tietze and Ch. Schenk; 8th Revised Edition; Springer Verlag Berlin (1986), pages 207-208 that gates can have a Tristate output.
“Selbsttest digitaler Schaltungen” [“Self-test of digital circuits”]; M. Gerner et al.; Oldenbourg Verlag Munich Vienna (1990), pages 56 to 59, pages 74 to 82 and pages 120 to 124 discloses a self-test principle, a boundary scan principle and a test response evaluation.
WO 01/59466 discloses a test arrangement and a test method, the test arrangement having a coupling which is to be tested and which has one or more analog components.
FIG. 5 schematically illustrates a test system 500 having a semiconductor chip 501 to be tested in the standard scan test. The test system 500 has a vector memory 502, output terminals 503 and input terminals 504. Four scan chains 505 are illustrated schematically on the semiconductor chip 501. Each the scan chains has an input terminal 506 and an output terminal 507. During the standard scan test, each output terminal 503 of the test system 500 is coupled to an input terminal 506 of the scan chains 505 of the semiconductor chip 501 and during the standard scan test, each output terminal 507 of the scan chains 505 of the semiconductor chip 501 is coupled to an input terminal 504 of the test system 500.
If, by means of the output terminals 503 of the test system 500, test signals are fed to the input terminals 506 of the scan chains 505 of the semiconductor chip 501 during the first shift phase of the scan test, the semiconductor chip 501 generates partial actual value signals during the subsequent normal phase. These signals together form the actual value signal. The partial actual value signals are then compared in the second shift phase by means of the output terminals 507 of the scan chains 505 of the semiconductor chip 501 in the input terminals 504 of the test system 500 with the previously stored determined desired value signal (expected responses) from the vector memory 502 in the test system 500. Both the signals of the test signal sequence and the desired value signal of the semiconductor chip 501 were stored in the vector memory 502. Information about the difference between desired value signal and actual value signal is stored in the test system 500 for analysis. The analysis is carried out by means of the test system 500.
One problem that arises in the case of the scan test in accordance with the prior art is that the test system can only react slowly in the case of an error. An error may be if the comparison with the expected responses from the vector memory 502 reveals that an actual value signal does not match the corresponding desired value signal. This is caused by signal propagation times between the semiconductor chip 501 and the test system 500, called the round trip delay.
In addition, a test system pipeline of the vector memory is first completely processed before the test system 500 can establish whether an error has occurred and can react thereto. The fastest possible reaction is desired, however, in order that all the data which are used for an error analysis are also available as soon as it is determined that an error has occurred. In other words, it is desirable to avoid the situation in which the storing components of the semiconductor chip 501 undergo transition to a different state compared with the state that represents an error in the respective electronic component. This cannot be ensured by means of the above-described test system 500 in accordance with the prior art since, in the time interval between the generation of the partial actual signal representing an error and the establishment of an error and reaction by the test system 500, the storing components have already changed their states.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.